CXAtmPhy-MIB: View SNMP OID List / Download MIB

Used to determine current MIB module release supported by agent. Object is in decimal.

A table containing information pertaining to one ATM PHY interface.

Defines an entry in the ATM PHY interface table.

Defines how the physical line's transmit clock will be derived. For DS1 and E1 ATM implementations, this object defines the interface clocking, and the corresponding clocking object at the DS1 and E1 layer becomes ineffective. This is contrary to non-ATM implementations where it is the clocking object at the DS1 and E1 layer that defines the interface clocking. Options: synchronized (1): The transmit clock will be derived from the receive clock. This is more commonly referred to as 'loop' timing. unsynchronized (2): The transmit clock will be derived internally from an oscillator, and will not be synchronized to the receive clock. Enumeration: 'unsynchronized': 2, 'synchronized': 1.

Defines the type of loopback mode. Options: none (1): Normal operating mode. All received cells are sent to the ATM layer. line (2): All received cells are re-transmitted immediately. Received cells are not processed and are not sent to the ATM layer. This setting has no effect for E1 cards. cell (3): All received cells are first processed and then passed to the transmitter to be sent back out. Received cells are not sent to the ATM layer. Enumeration: 'cell': 3, 'none': 1, 'line': 2.

Defines the type of framing used at this interface. Options: g-804 (1): ATM direct cell mapping as per ITU Recommendation G.804. plcp (2): ATM Physical Layer Convergence Protocol (PLCP) cell mapping as per Bellcore TR-TSV-000773. Enumeration: 'g-804': 1, 'plcp': 2.

Defines whether all internal FIFOs are bypassed when this interface is configured for the PLCP framing format (object atmPhyConfFrameFormat value 'atmPlcp'). FIFO bypass can be used to reduce latency at this interface (through the PHY device). This object will take on value 'disabled' in the initial phase since the ATM layer does not support cell rate decoupling, and idle/unassigned cell processing.

Defines whether the coset polynomial is applied to the HCS octet of transmitted cells. If 'enabled', the polynomial X^6+X^4+X^2+1 is added to the HCS octet of each cell prior to transmission as required by the ATM Forum UNI specification. The coset function prevents the HCS octet within a cell from taking on a zero value.

Defines whether the coset polynomial is applied to the HCS octet of received cells before comparisons. If 'enabled', the polynomial X^6+X^4+X^2+1 is removed from the HCS octet of each received cells before comparison with the calculated result as required by the ATM Forum UNI specification. The coset function prevents the HCS octet within a cell from taking on a zero value.

Defines whether the cell payload scrambling is applied to transmitted cells at this interface. If 'enabled', cell payloads are scrambled using the self synchronizing polynomial X^43+1. If 'disabled', cell payloads are transmitted unscrambled.

Defines whether received cell payloads are descrambled. If 'enabled', received cell payloads are descrambled using the self synchronizing polynomial X^43+1. If 'disabled', cell payload are not descrambled.

Defines the size of the transmit FIFO in cells. Reducing the FIFO depth permits cell latencies to be minimized at this interface (through the PHY device). It is not recommended that the FIFO depth be set to 1 cell, since half the bandwidth will be lost to idle/unassigned cells. For minimum latency and maximum throughput, a FIFO depth of 2 cells is suggested..

Defines the bit mask pattern for the first octet (H1) of a received cell. For each mask bit that is set, the PHY will process received cells with the corresponding bit(s) set in the H1 octet. For each mask bit that is reset, the PHY will discard received cells with the corresponding bit(s) set in the H1 octet. A logical OR is performed across all mask bits within the same mask byte, and across all four mask bytes.

Defines the bit mask pattern for the second octet (H2) of a received cell. For each mask bit that is set, the PHY will process received cells with the corresponding bit(s) set in the H2 octet. For each mask bit that is reset, the PHY will discard received cells with the corresponding bit(s) set in the H2 octet. A logical OR is performed across all mask bits within the same mask byte, and across all four mask bytes.

Defines the bit mask pattern for the third octet (H3) of a received cell. For each mask bit that is set, the PHY will process received cells with the corresponding bit(s) set in the H3 octet. For each mask bit that is reset, the PHY will discard received cells with the corresponding bit(s) set in the H3 octet. A logical OR is performed across all mask bits within the same mask byte, and across all four mask bytes.

Defines the bit mask pattern for the third octet (H4) of a received cell. For each mask bit that is set, the PHY will process received cells with the corresponding bit(s) set in the H4 octet. For each mask bit that is reset, the PHY will discard received cells with the corresponding bit(s) set in the H4 octet. A logical OR is performed across all mask bits within the same mask byte, and across all four mask bytes.

Defines the pattern inserted in the idle/unassigned cell payload. Idle/unassigned cells are inserted at this interface when the PHY device detects that the transmit FIFO contains no outstanding cells. The default pattern is 6AH, as defined by the ATM Forum UNI Specification.

Defines the duration, in milliseconds, permitted for PCLP error generation controls specified by object 'atmPhyConfPlcpControl'.

Defines the generic controls permitted at this interface. Interface. Options: none (1): The value returned following a 'clearStats' command. clearStats (2): Clear all statistics stored by statistics objects maintained within the Interface Operation and Interface Operational PLCP group tables. enableHCSErrorGeneration (3): Enables the insertion of an incorrect Header Error Checksum (HCS) within consecutive transmitted cells (assigned or unassigned). disableHCSErrorGeneration (4): Disables the insertion of an incorrect Header Error Checksum (HCS) within consecutive transmitted cells (assigned or unassigned). Enumeration: 'none': 1, 'enableHCSErrorGeneration': 3, 'clearStats': 2, 'disableHCSErrorGeneration': 4.

Defines the PLCP error generation controls permitted at this interface. This object is bit-mapped and can permit a maximum of 8 simultaneous error controls. Once the controls are initiated, the selected errors are generated for a period of time specified by object 'atmPhyConfPlcpControlTimer'. Error generation can be restarted at any time. To enable a specific control, its bit must be set. To disable a specific control, its bit must be reset. The controls are assigned the following bits: (bit-0): Controls the generation of a PLCP yellow alarm signal by setting the yellow signal bit position in the path status octet (G1) within consecutive PLCP frames. (bit-1): Controls the generation of a PLCP Far End Block Errors (FEBE) by inserting a single far end block error within consecutive PLCP frames. (bit-2): Controls the generation of PLCP Bit Interleave Parity (BIP) errors by inserting a single bit interleave parity error within consecutive PLCP frames. (bit-3): Controls the generation of frame alignment pattern errors by inserting a single bit error in each A1 & A2 octets within consecutive PLCP frames. (bit-4): Controls the generation of parity errors by inserting a parity error into each path overhead identification (POHID) octet within consecutive PLCP frames.

A table containing operational information and controls pertaining to one ATM PHY interface.

Defines an entry in the ATM PHY operational table.

Identifies the version level of the S/UNI-PDH. The second version of the device should return value 1.

Identifies the actual hardware framer detected. Only framers on ATM cards are detectable. Enumeration: 'none': 1, 'e1': 3, 'ds3': 4, 'e3': 5, 'ds1': 2.

Identifies the current state of the interface. Options: offline(1): Configuration for this interface has not yet been passed to the layer. downNoHwDetected (2): No ATM card was detected in order to support this configured. Interface. downConfigError (3): An ATM card was detected, however it is not the same as what was requested via configuration. down (4): An ATM card was detected, it matches the configuration requested, but the Physical Layers' PMD sublayer is currently down. up (5): This is the desired state. An ATM card was detected, it matches the configuration requested, and the Physical Layers' PMD sublayer is currently up. Enumeration: 'down': 4, 'offLine': 1, 'downConfigError': 3, 'downNoHwDetected': 2, 'up': 5.

Identifies the current cell delineation state of the interface, and only applies to an interface configured to used the direct mapping frame format (object atmPhyConfFrameFormat value 'g-804'). A Loss of Cell Delineation state is declared once an Out of Cell Delineation (OCD) defect has persisted for a default period of 99.4ms for a DS1 interface, or 76.9ms for an E1 interface. An OCD defect is declared once 8 consecutive ATM cells have HEC violations, as per ITU-I.432. Enumeration: 'detectedLCD': 1, 'noLCD': 2.

Indicates the number of idle/unassigned cells that have been dropped at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of header check sequence (HCS) errors that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of Out of Cell Delineation (OCD) events that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ). An OCD event is declared and counted once seven consecutive ATM cells are received with Header Error Check (HEC) violations.

Indicates the number of receive FIFO overruns that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of transmit FIFO overruns that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

A table containing additional operational information and controls pertaining to one ATM PHY interface configured for PLCP mapping.

Defines an entry in the ATM PHY operational table for PLCP configured interfaces.

Indicates the current PLCP Out Of Frame (OOF) defect state at this interface. An OOF is declared when an error is detected in both the A1 and A2 octets or when 2 consecutive POHID octets are found in error. AN OOF is removed and framing is declared upon finding 2 valid, consecutive set of frmaing (A1 and A2) octets and 2 valid and sequential path overhead identifier (POHID) octets.

Indicates the current PLCP Loss Of Frame (LOF) defect state at this interface. An LOF is declared when an OOF state persists for more than 25ms for DS1, or 20ms for E1 OLCP formats. When LOF is declared, PLCP reframe is initiated. An LOF is removed when an in-frame state persists for more than 250ms for DS1, or 200ms for E1..

Indicates the current PLCP Yellow Alarm (YA) defect state at this interface. A Yellow Alarm is declared when 10 consecutive yellow signal bits are set to logical 1. A Yellow Alarm is remove when 10 consecutive received yellow signal bits are set to logical 0.

Indicates the number of PLCP Out of Frame (OOF) defects detected or removed at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of PLCP Loss of Frame (LOF) defects detected or removed at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of PLCP Yellow Alarm (YA) defects detected or removed at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of PLCP Bit Interleaved Parity (BIP) errors that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of PLCP framing pattern octet errors and path overhead identification octet errors that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).

Indicates the number of PLCP Far End Block Errors (FEBE) that have been detected at this interface since the last power-up reset, or, since the statistics were last cleared (via object atmPhyConfControl value 'clearStats' ).