ADN-ENV-MIB: View SNMP OID List / Download MIB

This table is internal for use by FRANP Signalling for the purpose of debugging.

An entry in the Signalling Trunk Channel Table. There will be one entry for each FRANP Signalling Trunk channel configured. This table will also be indexed by adnFrtChanSiIndex in order to be able to access individual trace entries.

This entry represents the current instance or index of the table. It is provided in order to be able to dump each instance of each object.

This timer specifies the amount of time to wait for a resource available message to be sent to FRANP Path Select SwBB. If the timer expires, then the message is transmitted. This is expressed in SECONDS. The timer may be set by SNMP command.

The threshold value is specified as a percentage of the BAT. If the available bandwidth drops below this threshold, the resource available message sent to FRANP Path Select component. The value may be set by SNMP command.

This is the internal BINARY trace area for call control information trace area, maintained by FRANP_SI. It is placed here for maintenance purposes only.

This object provides a mechanism for controlling Franp Signalling ability to enable/disable tracing data from its Bus side, Trunk side, and Ism side. The following are the possible values it can hold. 1 - Trace activity enabled (normally is defaulted on) 2 - Trace activity disabled

This object provides a mechanism for defining the number of entries the Franp Signalling trace area can have. Be aware when issuing a set command to modify this value, any existing trace data will be lost to make room for the new trace block size.

This is the internal BINARY message trace entry maintained by FRANP_SI for its 3 main interfaces, (Bus side, Trunk side, and Ism side). This entry is instantiated by AdnFrtChanSiInstance index that comprises the entire trace area table. The FRANP Signalling software is implemented as a Finite State Machine, and all message events received are stored here. It is placed here for maintenance purposes only.

This is the internal BINARY statistic trace table maintained by FRANP_SI for this Bus Side interface. The Franp Signalling software is implemented as a Finite State Machine, and all statistics collected are stored here. It is placed here for maintenance purposes only.

This is the internal BINARY statistic trace table maintained by FRANP_SI for this Trunk Side interface. The Franp Signalling software is implemented as a Finite State Machine, and all statistics collected are stored here. It is placed here for maintenance purposes only.

This is the internal BINARY call reference active trace maintained by FRANP_SI for this Bus Side interface. It is placed here for maintenance purposes only.

This is the internal BINARY call reference active trace maintained by FRANP_SI for this Trunk Side interface. It is placed here for maintenance purposes only.

This is the internal BINARY Bandwidth Information table maintained by FRANP_SI for this Trunk Side interface. It is placed here for maintenance purposes only.

This field is used to calculate the minimum delay change a periodic delay measurement can consider to be significant. Such significant delay changes may result in a new delay reported to ROUTES. The minimum delay change is calulated by multiplying this field as a percentage times the delay measured immediately after a RESTART/RESTART ACK exchange.

If the minimum delay change calculated using adnFrtChanSiMinDlyPct is less than this field, the minimum delay change a periodic delay measurement can consider to be significant is set equal to this field instead of the calculated value.

Before a periodic delay measurement can report a new delay value to ROUTES, a specified number of consecutive measurements must be significantly high OR a specified number of consecutive measurements must be significantly low. This field defines that specified number of consecutive measurements.

This table contains internal channel level information for FRANP_SW. There is no existing standard MIB for Alcatel internal network protocol.

An entry in the internal FRANP Switching Channel Table. There will be one entry for each FRANP channel configured

This is the BINARY internal channel structure maintained by FRSI portion of FRANP_SW for this channel. It is placed here for maintenance purposes only.

This is the BINARY internal channel structure maintained by TPX/F IWF portion of FRANP_SW for this channel. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by FRSI portion of FRANP_SW for this channel. It is placed here for maintenance purposes only.

This is the PVC table for FRANP trunk protocol.

PVC table entry

This is the Bus Side Interface call reference associated with the VC.

Define here are the state that are implemented and supported for the FRANP Signalling bus Side Interface.

This is the Trunk Side Interface call reference associated with the VC.

Define here are the state that are implemented and supported for the FRANP Signalling Trunk Side Interface.

This is the local Suid associated with the VC.

This is the local LPX associated with the VC.

This is the local Maximum Congestion Monitoring Period associated with the VC.

This is the local Application reference number associated with the VC.

This is the local Data Handler reference number associated with the VC.

This is the local Franp Signalling reference number associated with the VC.

This indicates the ifindex of the remote Chassis/Slot/ Port/Channel.

This is the remote Suid associated with the VC.

This is the remote Lpx associated with the VC.

This is the remote Maximum Congestion Monitoring period associated with the VC.

This is the remote Application reference number associated with the VC.

This is the remote Data Handler reference number associated with the VC.

This is the remote Franp Signalling reference number associated with the VC.

This indicates the ifindex of the remote Chassis/Slot/ Port/Channel.

This is the timer ID that is currently running for this VC.

This is the timer ID that is currently running for this VC.

This is the number of times this Bus Side Interface timer ID has expired.

This is the number of times this trunk Side Interface timer ID has expired.

This is the internal VC table for FRANP Switching.

PVC table entry

This is the BINARY internal VC structure maintained by the FRSI portion of FRANP_SW. It is placed here for maintenance purposes only.

This is the BINARY internal VC structure maintained by the TPX/F IWF portion of FRANP_SW. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by the FRSI portion of FRANP_SW for this VC. It is placed here for maintenance purposes only.

This is the FRANP Signalling table. It will exists once per FRANP Signalling instance on each LT.

One instance of the adnFrtSiTable. There will be one instance for each FRANP Signalling on each LT.

This entry represents the current instance or index. It is provided in order to be able to dump each Franp_si trace instance of each object.

This object provides a mechanism for controlling Franp Signalling ability to enable/disable tracing data from its Bus side, Trunk side, and Ism side. The following are the possible values it can hold. 1 - Trace activity enabled 2 - Trace activity disabled (default setting)

This object provides a mechanism for defining the number of entries the Franp Signalling trace area can have. Be aware when issuing a set command to modify this value, any existing trace data will be lost to make room for the new trace block size.

This is the internal BINARY message trace entry maintained by FRANP_SI for its 3 main interfaces, (Bus side, Trunk side, and Ism side). This entry is instanciated by AdnFrtSiInstance index that comprises the entire trace area table. The FRANP Signalling software is implemented as a Finite State Machine, and all message events received are stored here. It is placed here for maintenance purposes only.

This is the internal FRANP_SI data structure. This will contain internal error counters and structures. This is the internal table maintained by FRANP_SI.

This is the ISM message trace area. All ISM Messages transmitted and received by FRANP_SI are stored here. It is placed here for maintenance purposes only.

This is the FRANP_SW table. It will exists once per FRANP_SW instance on each LT.

One instance of the adnFrtSwTable. There will be one instance for each FRANP_SW on each LT.

This is the internal FRSI data structure. This will contain internal error counters and structures. This is the internal table maintained by FRSI component of FRANP_SW.

This is the internal IWF data structure. This will contain internal error counters and structures. This is the internal table maintained by IWF component of FRANP_SW.

This is the ISM message trace area. All ISM Messages transmitted and received by FRSI component of FRANP_SW are stored here. It is placed here for maintenance purposes only.

This table is an extension of the Frame Relay Management Signalling Group table and the Frame Relay Logical Port Group table from RFC1604.

An entry in the Channel Table. There will be one entry for each FRS channel configured

This is the BINARY internal channel structure maintained by FRS_SW. It is placed here for maintenance purposes only.

This is the BINARY internal channel structure maintained by FRS_SI. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by FRS_SW for this channel. The FRS_SW software is implemented as a Finite State Machine, and all events received and their corresponding states are stored here. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by Channel Management portion of FRS_SI for this VC. The Channel Management software is implemented as a Finite State Machine, and all events received and their corresponding states are stored here. It is placed here for maintenance purposes only.

This is the PVC table extensions. The PVC End-Point Table in RFC1604 is not sufficient for our HSS network. These fields are the extensions to it

PVC table entry

This is the BINARY internal PVC structure maintained by FRS_SW. It is placed here for maintenance purposes only.

This is the BINARY internal PVC structure maintained by FRS_SI. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by FRS_SW for this VC. The FRS_SW software is implemented as a Finite State Machine, and all events received and their corresponding states are stored here. It is placed here for maintenance purposes only.

This is the internal BINARY message trace table maintained by PVC handler portion of FRS_SI for this VC. The PVC handler software is implemented as a Finite State Machine, and all events received and their corresponding states are stored here. It is placed here for maintenance purposes only.

This is the FRS table. It will exists once per FRS instance on each LT.

One instance of the adnFRSTable. There will be one instance for each FRS on each LT.

This is the internal FRS data structure. This will contain internal error counters and structures. This is the internal table maintained by FRS_SI.

This is the internal FRS data structure. This will contain internal error counters and structures. This is the internal table maintained by FRS_SW.

This is the ISM message trace area. All ISM Messages transmitted and received by FRS_SI are stored here.

This is the LDR software building block table. Each LDR on each LT has one. It mainly contains debug information.

There will be one instance for each LDR on each LT.

This is the internal LDR data structure. It contains the internal error counters and other information of the LDR Software status. This is the internal table maintained by LDR.

This is the ISM message trace area. All ISM Messages transmitted and received by FRS_SI are stored here.

This table contains internal channel structure maintained by LDR. It is used for maintenance purposes only.

An entry in the LDR Channel Environment Table. There will be one entry for each LDR channel configured.

Flag indicating if trace is enabled.

This is the BINARY channel control block data structure maintained by the LDR. It is placed here for maintenance purposes only

This is the trace area for LDR and CME-SUP interface. The information of messages that sent and received by the LDR are stored here.

This is the trace area for LDR and INMP Library interface. Function call information (LDR functions called by INMP Library, and functions in INMP Library called by LDR) are recorded here.

This is the ISNA Internal Connection diagnostic table definitions. It is an extension to the adnIsnaIcTable definitions.

Internal ISNA IC level diagnostic table. Uses indeces adnIsnaIcifIndex and adnIsnaIcDlci defined in adnIsnaIcTable table.

This object defines the 1st half of the Internal Connection defined in the adnIsnaIcTable and is one to one mapping to adnIsnaIcifIndex object.

This object defines the 2nd half of the Internal Connection defined in the adnIsnaIcTable and is one to one mapping to adnIsnaIcDlci object.

The total number of packets transmitted by ISNA to the IP layer that are associated with a given Internal Connection

The total number of packets received by ISNA from the IP layer that are associated with a given Internal Connection

The total number of ISS status packets transmitted by ISNA to ISOM that are associated with a given Internal Connection

The total number of ISS status packets received by ISNA from ISOM that are associated with a given Internal Connection

The total number of ICMP packets received by ISNA from the local IP layer that are associated with a given Internal Connection

The total number of ICMP packets transmitted by ISNA to the local IP layer that are associated with a given Internal Connection

The total number of IP packets destined to IP layer, discarded due to internal IP access failures or system resources errors. All packets discarded are associated with a given Internal Connection.

The total number of IP packets received from IP layer, discarded due to internal ICS access failures or system resources errors. All packets discarded are associated with a given Internal Connection.

This is the internal BINARY message trace table maintained by ISNA for this IC/PVC. The ISNA software is implemented as a Finite State Machine, and all events received and their corresponding states are stored here. It is placed here for maintenance purposes only.

This is the ISNA IP diagnostic table definitions.

ISNA IP Trafic counters level diagnostic table. Uses index adnIsnaIpIndex defined in adnIsnaIpTable table.

This object is mapped to adnIsnaIpIndex in the adnIsnaIpTable.

The total number of LPXs (logical processor index) in IIRT (IP ISNA routing table) table.

The total number of Interfaces in IIRT (IP ISNA routing table) table.

The total number of VCs in IIRT (IP ISNA routing table) table.

The total number of packets transmitted by ISNA_IP to the IP layer.

The total number of packets received by ISNA_IP from the IP layer.

The total number of discarded IP packets coming from IP layer.

The total number of packets transmitted by ISNA_IP to IPOM sybsystem.

The total number of packets received by ISNA_IP from IPOM subsytem.

The total number of discarded IP packets comming from IPOM subsystem.

The total number of packets received by ISNA_IP from RDSS subsytem.

The total number of packets transmitted by ISNA_IP to RDSS sybsystem.

The total number of discarded IP packets comming from RDSS subsystem.

This is the ISNA IP IIRT (IP ISNA routing table) tree table definitions.

ISNA IP IIRT (IP ISNA routing table) tree entry table. Uses index adnIsnaIpIirtIpaddrs defined in adnIsnaIpIirtTable table.

The next hop IP address .

The VC number on the local Interface, The NHIPA (next hop IP address) apply to the remote interface which the VC is connecting.

The ifindex Interface at the local machine.

The LPX (logical processor index) local which the interface is configured on.

The session id which IP packet is routed to.

The status of the VC (up or down) which associate with NHIPA (next hop IP address.

This is the board miscellaneous characteristics table.

An entry in the Board Miscellaneous characteristics Table. There is one entry for each Board. The index corresponds to equipment type card in the adnEquipTable.

This object contains the characteristics of the board retrieved through the ISL link. This object is a dump of 256 bytes of the EEPROM of the board, It contains information called group 2 information. The signification of each byte is detailed in the document 8BA00940001ASZZA. When the board is not plugged in, the value of this object is 00 00 00 00 ( that is, an octet string of length 4, with each octet having a zero decimal value).

This table is the ATM boards error counter table. Each counter corresponds to a defect number identified by a bit set in the adnAtmBoardASEStatus for ASe board, the adnAtmBoardCIGStatus for CIG board and the adnAtmBoardHSCStatus for HSC board. These nominators are defined in the adnAtmBoardErCounterTable. The counters are classified according to the board type. Some are specific to the broadband ATM switching element (BBASE) board also called the matrix board.

An entry in the ATM boards error counter table.

The counter associated with the number of user FIFO overflows; counter #0 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of user FIFO read failures; counter #1 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of network FIFO overflows; counter #2 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of BGPHT chip RAM parity errors; counter #3 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of network FIFO read failures; counter #4 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of cells received on non active VC; counter #5 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of cells received on non active VP; counter #6 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of reception buffer overflows; counter #7 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of QRP 0 chip RAM parity errors; counter #14 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 0 chip DMA errors; counter #15 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 0 chip extraction FIFO overflows; counter #16 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 1 chip RAM parity errors; counter #17 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 1 chip DMA errors; counter #18 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 1 chip extraction FIFO overflows; counter #19 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 2 chip RAM parity errors; counter #20 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 2 chip DMA errors; counter #21 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 2 chip extraction FIFO overflows; counter #22 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 3 chip RAM parity errors; counter #23 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 3 chip DMA errors; counter #24 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of QRP 3 chip extraction FIFO overflows; counter #25 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of low priority cells lost due to SCD; counter #26 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of high priority cells lost due to buffer overflow(FULC); counter #27 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of fault synchronization in the HMP 0 chip; counter #28 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of low priority cells lost in the HMP 1 chip; counter #29 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of high priority cells lost in the HMP 1 chip; counter #30 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of fault synchronization in the HMP 1 chip; counter #31 of the ATM core; this counter is only relevant for the matrix board.

This table is the ATM boards traffic counter table. The counters are classified according to the board type. Some are specific to the broadband ATM switching element (BBASE) board also called the matrix board.

An entry in the ATM boards traffic counter table.

The counter associated with the observation threshold 1 crossing of the HMP 0 chip; counter #0 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the observation threshold 2 crossing of the HMP 1 chip; counter #1 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of free outgoing point-to-multipoint (PTM) internal channel identifiers (ICI); counter #2 of the ATM core; this counter is only relevant for the matrix board.

This table is the ATM electrical interface (AEI) port error counter table. Each counter corresponds to a defect number identified by a bit set in the adnAtmPortASEStatus for ASe board, the adnAtmPortCIGStatus for CIG board and the adnAtmPortHSCStatus for HSC board. These nominators are defined in the adnAtmPortErCounterTable. The counters are classified according to the board type. Some are specific to the broadband ATM switching element (BBASE) board also called the matrix board.

An entry in the ATM electrical interface (AEI) port error counter table.

The counter associated with the out of synchronization intervals; counter #0 of the ATM core.

The counter associated with the loss of synchronization intervals; counter #1 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of network FIFO overflows; counter #2 of the ATM core.

The counter associated with the number of BGIEM chip RAM parity errors; counter #3 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of correctable errors on cells header; counter #4 of the ATM core.

The counter associated with the number of uncorrectable errors on cells header; counter #5 of the ATM core.

The counter associated with the number of CRC errors on payload field of maintenance active cells of type 1 (MA1); counter #6 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of CRC errors on payload field of self identified cells (SIC); counter #7 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of parity errors on payload field of cells; counter #8 of the ATM core.

The counter associated with the number of unallowed routing tags; counter #9 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of lost data maintenance cells; counter #12 of the ATM core.

The counter associated with the number of data maintenance cells received with error; counter #14 of the ATM core.

The counter associated with the number of network/signalling FIFO overflows; counter #17 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of network FIFO write failures; counter #18 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of signalling FIFO write failures; counter #19 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of network/signalling FIFO read failures; counter #20 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of user/signalling FIFO read failures; counter #22 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of user FIFO write failures; counter #23 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of user/signalling FIFO overflows; counter #24 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of cells received on non active internal channel identifier (ICI); counter #25 of the ATM core.

The counter associated with the number of CRC errors on network side; counter #26 of the ATM core.

The counter associated with the number of ATM adaptation layer (AAL) sequence errors on network side; counter #27 of the ATM core.

The counter associated with the number of CRC errors on user side; counter #28 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of ATM adaptation layer (AAL) sequence errors on user side; counter #29 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of unrouted cells; counter #30 of the ATM core; this counter is only relevant for the matrix board.

This table is the ATM electrical interface (AEI) port traffic counters table. The counters are classified according to the board type. Some are specific to the broadband ATM switching element (BBASE) board also called the matrix board.

An entry in the ATM electrical interface (AEI) port traffic counters table.

The counter associated with the number of point-to-point (PTP) setup requests; counter #1 of the ATM core.

The counter associated with the number of point-to-multipoint (PTM) setup requests; counter #2 of the ATM core.

The counter associated with the number of point-to-point (PTP) setup rejects due to blocking; counter #3 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) setup rejects due to blocking; counter #4 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) setup rejects due to communication; counter #5 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) setup rejects due to communication; counter #6 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) setup trials; counter #7 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) setup trials; counter #8 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) connections in progress; counter #13 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) connections in progress; counter #14 of the ATM core; this counter is not relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) bandwith or internal channel identifier (BW,ICI) requests; counter #4 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) bandwith or internal channel identifier (BW,ICI) requests; counter #5 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) bandwith (BW) requests failure; counter #6 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) bandwith (BW) requests failure; counter #7 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of point-to-point (PTP) internal channel identifier (ICI) requests failure; counter #8 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of point-to-multipoint (PTM) internal channel identifier (ICI) requests failure; counter #9 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the reserved peak bandwith (BW); counter #10 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of free point-to-point (PTP) internal channel identifiers (ICI); counter #12 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the reserved mean priority bandwith (BW); Counter #14 of the ATM core; this counter is only relevant for the matrix board.

The counter associated with the number of incoming cells; counter #15 of the ATM core.; this counter is only relevant for the matrix board.

The counter associated with the number of outgoing cells; counter #16 of the ATM core; this counter is only relevant for the matrix board.

This table is the ATM boards defects table. Some defects characteristics are updatable. Matrix board case: all the defects are only readable.

An entry in the ATM boards defects table. There will be one entry for each defect (i.e error/warning) configured. Notice that according to the defect number, default value of each parameter of the instance may be different between two instances.

This is the ATM board type.

This indicates the defect number. The description of each defect is given via the adnAtmBoardErASEStatus for ASE board, the adnAtmBoardErHSCStatus for HSC board, the adnAtmBoardErCIGStatus for CIG board. These nominators are defined in the adnAtmBoardErTable. Theres a one to one mapping between the bit position and the defect number.

This indicates the event class from hardware side: event: single fault signalled by the hardware or another software module to the supervision antenna inside the coupler board. No end is signalled, the presence of the fault cant be checked. status: the beginning of the fault is signalled to the supervision antenna inside the coupler board; the presence of the fault can be checked. statusc: the hardware provides no interrupt; this status is periodically scanned by the supervision antenna inside the coupler board. counter: a n bit long hardware counter counts the elementary events; an interrupt is generally sent at saturation; its value can be read; it is reset to zero when read.

This indicates the number of times an error is detected within a time period (defined by adnAtmBoardDefBegTimer) before an event (beginning of error) is generated and an error condition is entered.

This indicates the maximum number of times a condition may be detected within a time period (defined by adnAtmBoardDefEndTimer) before an event (ending of error) is generated and an error condition is cleared.

This indicates the beginning timer in milliseconds during which the first appearance of an error is controlled.

This indicates the end timer in milliseconds during which the disappearance of an error is controlled.

This indicates the defect signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The various bit positions are: 1 : ERI (error indicator, bit inserted in the active maintenance cells to warn neighbour boards that an error is detected), 2 : P-FERF or RDI-P (path section far end received failure indication sent to the origin of the defect), 4 : MS-FERF or RDI-L (multiplexing section far end received failure indication sent to the origin of the defect), 8 : ATM-AIS (alarm indication signal is sent on a line defect towards the network handler dealing with VP/VC AIS management), 16 : RAI (remote alarm indication), 32 : RLED (the status led must be set permanent red).

This indicates the defect type (i.e error or warning); an error is a critical defect which modifies the operational state of the object.

This indicates the report control of the defect towards the control unit (CU).

This table is the ATM electrical interface (AEI) port defects table. Some defects characteristics are updatable. Matrix board case: all the defects are only readable.

An entry in the ATM electrical interface (AEI) port defects table. There will be one entry for each defect (i.e error/warning) configured. Notice that according to the defect number, default value of each parameter of the instance may be different between two instances.

This is the ATM board type.

This indicates the defect number. The description of each defect is given via the adnAtmPortErASEStatus for ASE board, the adnAtmPortErHSCStatus for HSC board, the adnAtmPortErCIGStatus for CIG board. These nominators are defined in the adnAtmPortErTable. Theres a one to one mappingbetween the bit position the defect number.

This indicates the event class from hardware side: event: single fault signalled by the hardware or another software module to the supervision antenna inside the coupler board. No end is signalled, the presence of the fault cant be checked. status: the beginning of the fault is signalled to the supervision antenna inside the coupler board; the presence of the fault can be checked. statusc: the hardware provides no interrupt; this status is periodically scanned by the supervision antenna inside the coupler board. counter: a n bit long hardware counter counts the elementary events; an interrupt is generally sent at saturation; its value can be read; it is reset to zero when read.

This indicates the direction of the defect when it occurs.

This indicates the number of times an error is detected within a time period (defined by adnAeiPortDefBegTimer) before an event (beginning of error) is generated and an error condition is entered.

This indicates the maximum number of times a condition may be detected within a time period (defined by adnAeiPortDefEndTimer) before an event (ending of error) is generated and an error condition is cleared.

This indicates the beginning timer in milliseconds during which the first appearance of an error is controlled.

This indicates the end timer in milliseconds during which the disappearance of an error is controlled.

This indicates the defect signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The various bit positions are: 1 : ERI (error indicator, bit inserted in the active maintenance cells to warn neighbour boards that an error is detected), 2 : P-FERF or RDI-P (path section far end received failure indication sent to the origin of the defect), 4 : MS-FERF or RDI-L (multiplexing section far end received failure indication sent to the origin of the defect), 8 : ATM-AIS (alarm indication signal is sent on a line defect towards the network handler dealing with VP/VC AIS management), 16 : RAI (remote alarm indication), 32 : RLED (the status led must be set permanent red).

This indicates the defect type (i.e error or warning); an error is a critical defect which modifies the operational state of the object.

This indicates the report control of the defect towards the control unit (CU).

This table is the ATM line defects table.

An entry in the ATM line errors/warnings and defects table. There will be one entry for each defect (error/warning) configured. Notice that according to the defect number, default value of each parameter of the instance may be different between two instances.

This is the line type.

This indicates the defect number.

This indicates the event class from hardware side: event: single fault signalled by the hardware or another software module to the supervision antenna inside the coupler board. No end is signalled, the presence of the fault cant be checked. status: the beginning of the fault is signalled to the supervision antenna inside the coupler board; the presence of the fault can be checked. statusc: the hardware provides no interrupt; this status is periodically scanned by the supervision antenna inside the coupler board. counter: a n bit long hardware counter counts the elementary events; an interrupt is generally sent at saturation; its value can be read; it is reset to zero when read.

This indicates if the defect is used or not in performance calculation. If the defect is used for the performance calculation (i.e DefUseInPerfCalcul = yes), then the type of this defect (DefPerfType) from performance side can be either: defect: then, each occurence of the defect contributes to the performance calculation, counter: then, a counter is used to take into account this defect in performance calculation when the threshold defined by DefPerfThr is reached.

This indicates the performance type : counter: a counter is used to take into account this defect in performance calculation when the threshold defined by DefPerfThr is reached, defect: each occurence of the defect contributes to the performance calculation, defectc: each occurence of the defect contributes to the performance calculation, with counting of seconds (ANSI only).

This indicates the threshold value of the performance counter.

This indicates the direction of the defect when it occurs: transmit: defect on transmission direction, receive: defect on reception direction, without inhibition of transmission counters, receiveInhib: defect on reception direction, with inhibition of transmission counters.

This indicates the number of times an error is detected within a time period (defined by adnAtmLineDefBegTimer) before an event (beginning of error) is generated and an error condition is entered.

This indicates the maximum number of times a condition may be detected within a time period (defined by adnAtmLineDefEndTimer) before an event (ending of error) is generated and an error condition is cleared.

This indicates the beginning timer in milliseconds during which the first appearance of an error is controlled.

This indicates the end timer in milliseconds during which the disappearance of an error is controlled.

This indicates the failure signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The various bit positions are: 1 : ERI (error indicator, bit inserted in the active maintenance cells to warn neighbour boards that an error is detected), 2 : P-FERF or RDI-P (path section far end received failure indication sent to the origin of the defect), 4 : MS-FERF or RDI-L (multiplexing section far end received failure indication sent to the origin of the defect), 8 : ATM-AIS (alarm indication signal is sent on a line defect towards the network handler dealing with VP/VC AIS management), 16 : RAI (remote alarm indication), 32 : RLED (the status led must be set permanent red).

This indicates the defect type (i.e error or warning); an error is a critical defect which modifies the operational state of the object.

This indicates the report control of the defect towards the control unit (CU).

This indicates the current Defect hierarchy towards the other defects; it is coded as a long integer (i.e 32 bits). Theres one bit per defect: - bit #n = 0 : defect n masked (i.e the current defect inhibits the #n one if both are present), - bit #n = 1 : defect n unmasked.

This indicates the level at which the defect is managed: line: the defect is managed at line level, path: the defect is managed at path level.

This indicates the failure signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The various bit positions are: 1 : ERI or RSA (error indicator, bit inserted in theactive maintenance cells to warn neighbour boards that an error is detected), 2 : P-FERF or RDI-P or RAI (path section far end received failure indication sent to the origin of the defect), 4 : MS-FERF or RDI-L (multiplexing section far end received failure indication sent to the origin of the defect), 8 : ATM-AIS (alarm indication signal is sent on a line defect towards the network handler dealing with VP/VC AIS management), 32 : RLED (the status led must be set permanent red).

This indicates the defect signalling in addition to the report towards the control unit (CU). It is coded as a bit map. The various bit positions are: 1 : ERI or RSA (error indicator, bit inserted in theactive maintenance cells to warn neighbour boards that an error is detected), 2 : P-FERF or RDI-P or RAI (path section far end received failure indication sent to the origin of the defect), 4 : MS-FERF or RDI-L (multiplexing section far end received failure indication sent to the origin of the defect), 8 : ATM-AIS (ATM alarm indication signal is sent on a line defect towards the network handler dealing with VP/VC AIS management), 32 : RLED (the status led must be set permanent red), 64 : NB-AIS (not ATM alarm indication signal is sent on a line defect towards the AEI side), 128 : TCK (trunk conditioning: in circuit emulation, a specified pattern is sent in timeslots, except TS0: a pattern for TS16, another one for other TS).

This table is the ATM line performance parameters table.

An entry in the ATM line performance parameters table. There will be one entry for each line type.

This is the line type.

This indicates the number of blocks sent and received per second.

This indicates the low second error block threshold; the value range of this threshold is 1..adnAtmLinePerfHighErrBlockThr.

This indicates the high second error block threshold; the value range of this threshold is 1..adnAtmLinePerfBlocksPerSec.

This indicates the number of consecutive severely erroned seconds necessary to declare the beginning of an unavailable period.

This indicates the number of consecutive non severely erroned seconds necessary to declare the ending of the unavailable period.

This indicates the number of consecutive severely errored seconds used for the F3 maintenance flow calculation.

This indicates the high threshold for background block error on 1/4 hour period; the value range of this threshold is 0..900*adnAtmLinePerfHighErrBlockThr.

This indicates the high threshold for errored second on 1/4 hour period; the value range of this threshold is 0..900.

This indicates the high threshold for severely errored second on 1/4 hour period; the value range of this threshold is 0..900.

This indicates the low threshold for background block error on 1/4 hour period; the value range of this threshold is 0..adnAtmLinePerfHighBBE15Thr.

This indicates the low threshold for errored second on 1/4 hour period; the value range of this threshold is 0..adnAtmLinePerfHighES15Thr.

This indicates the low threshold for severely errored second on 1/4 hour period; the value range of this threshold is 0..adnAtmLinePerfHighSES15Thr.

This indicates the threshold for background block error on 24 hours period; the value range of this threshold is 0..86400*adnAtmLinePerfHighErrBlockThr.

This indicates the threshold for errored second on 24 hours period; the value range of this threshold is 0..86400.

This indicates the threshold for severely errored second on 24 hours period; the value range of this threshold is 0..86400.

This table is the HSC Board Traffic Management parameters table. This is only relevant for HSC boards with output buffers

An entry in the ATM Traffic Management parameters table.

This indicates the line number the output buffer is assigned to.

This indicates the Explicit Forward Congestion Indication (EFCI) activation threshold in medium priority output buffer (OB); EFCI is generated towards the receiver termination point, in order to prevent congestion situation to be encountered within the output buffer; EFCI tagging is activated as soon as the activation threshold is reached; EFCI tagging is stopped as soon as the filling of the OB is below the EFCI desactivation threshold; the value range of the threshold is 0..adnHscBoardTrMgtMOBSize; this is not relevant for E1B and T1B boards.

This indicates the Explicit Forward Congestion Indication (EFCI) desactivation threshold in low priority output buffer (OB); EFCI is generated towards the receiver termination point, in order to prevent congestion situation to be encountered within the output buffer; EFCI tagging is activated as soon as the activation threshold is reached; EFCI tagging is stopped as soon as the filling of the OB is below the EFCI desactivation threshold; the value range of the threshold is 0..adnHscBoardTrMgtLOBSize; this is not relevant for E1B and T1B boards.

This table is the BBASE Board Traffic Management environment table; the index is the AEI port number of the BBASE; this is relevant only for the matrix board with adnEquipSubType equal to adnBbaseb.

An entry in the BBASE Board Traffic Management environment table.

This is BBASE AEI port number.

This indicates the speed of the AEI port ; the allowed values are : - speed622 : 622.08 Mb/s - speed603 : 603.23 Mb/s - speed593 : 593.80 Mb/s - speed565 : 565.53 Mb/s - speed155 : 155.52 Mb/s - speed150 : 150.81 Mb/s - speed148 : 148.45 Mb/s - speed142 : 142.00 Mb/s - speedLine : speed of the outgoing physical line ; this is relevant only for the matrix board with adnEquipSubType equal to adnBbaseb.

The Frame Relay LT Information table for Congestion Management.

An entry in the Frame Relay LT Information table . The line and channel portion of ifIndex is not significant.

flag indicating if trace per LT is enabled

This is the BINARY table that determines the congestion level based upon the percentage of free Cryspix Buffer descriptors. It is placed here so that the level could be changed to achieve fine tuning. It is placed here for debugging and maintenance purpose only

This is the processor utilization value of this LT as calculated by the congestion management. it is placed here for maintenance purpose only

The Frame Relay channel Information table for Congestion Management.

An entry in the Frame Relay Channel Information table.

This is the BINARY internal structure per channel maintained by congestion management. It contains the contents of the channel control block. It is placed here for maintenance purposes only.

This is the BINARY discard message trace table per channel maintained by congestion management. It contents the discard message received by this channel from other cards. It is placed here for maintenance purposes only.

This is the BINARY message trace table per channel maintained by congestion management. It contents the trace of all the messages received by this channel from the application. It is placed here for maintenance purposes only.

flag indicating if trace per channel is enabled

Current channel utilization value in the egress direction

This is the maximum of the egress channel utilization and the processor utilization. This field may be set to zero via SNMP command, so that the user may be able to measure or read the maximum CUF over a period of time.

This is the minimum time in microseconds needed to process a subframe. This value is used when calculating processor utilization.

This is the VC table for Frame Relay Congestion Management.

VC table entry

This is the BINARY internal PVC structure maintained by FRANP_SW. It is placed here for maintenance purposes only.

This is an internal BINARY message trace table maintained by congestion management for this VC. This trace will contain relevant info for each subframe comming from the Line and going to the bus. It is placed here for maintenance purposes only.

This is an internal BINARY message trace table maintained by congestion management for this VC. This trace will contain relevant info for each subframe comming from the Bus and going to the Line. It is placed here for maintenance purposes only.

value indicating if trace per VC is enabled

This is an internal BINARY message trace table maintained by congestion management for this VC. This trace will contain the state and events of the SIR update state machine and ISM congestion state machine. It is placed here for maintenance purposes only.

The Frame Relay LT Trace table for Congestion Management.

An entry in the Franp cm trace table

This is the trace area for the calendar queue related variables. It is placed here for maintenance purpose only

Index indicating the current index of Calendar Queue trace. This is used to display more than 255 bytes of trace by means of repeated getnext message from the INMP

This is the LAP private table. It will exist once per LAP instance on each LT.

One instance of the adnLapPrivateTable. There will be one instance for each LAP on each LT.

This identifies the enable state of the tracing option at the Level 1 interface.

This is internal Level 1 message trace BINARY buffer

This identifies the enable state of the tracing option at the Level 3 interface.

This is internal Level 3 message trace BINARY buffer

This identifies the enable state of the tracing option at the NMGS interface.

This is internal NMGSmessage trace BINARY buffer

This identifies the enable state of the tracing option for RASinfo.

The statistics, trace information and current states debug dump fields to be used for remote debugging information. RAS = reliability, accessibility, serviceability

SSUPCU maintained SM processor control blocks. There is one such block for every secondary module (SM) processor that has been created (configured). The SSUPCU will keep current status information about the remote processor (among many other things) in such a block.

This is a description of a single entry in the SSUPCU Processor control block table. For debugging reason, a hex-dump is considered sufficient for now. Structures defined in C-header files will be used to determine the values of the appropriate fields. The table exists only on the CU, and therefore uses the CENTRALIZED indexing for SFAS/MSUP routing purposes. The additional index will be encoded to adnProcessor type definition allow SSUPCU code to determine which instance is desired by the user.

This is the hex-dump that represents the SSUPCU processor control block entry. Each such entry contains information about a SM processor on a coupler card that is configured.

SSUPOM maintained SM processor control blocks. There is one such block per OM processor. Only a single instance is maintained in each OMs memory, that pertaining to itself. This block contains information needed for the functioning of the processor, as well as information relating to the LT processors on the card.

This is a description of a single entry in the SSUPOM Processor control block table. For debugging reason, a hex-dump is considered sufficient for now. Structures defined in C-header files will be used to determine the values of the appropriate fields. The adnCouplerIndex is used for SFAS/MSUP routing purposes. This unfortunately only contains information of the chassis, slot and _line_ number (not processor). The user has to be aware of what line would map to the OM processor. Currently the line should be encoded as 512. Note that this information is likely to change.

The defintion of the adnCouplerIndex object. It is used for routing the SNMP command to the appropriate processor by SFAS/MSUP sub-systems.

This is the hex-dump that represents the SSUPOM processor control block entry. Each such entry contains information about the OM processor in which memory the block resides.

SSUPLT maintained SM processor control blocks. There is one such block per LT processor. Only one block exists in each LT processors memory, and it contains information needed by that processor only.

This is a description of a single entry in the SSUPLT Processor control block table. For debugging reason, a hex-dump is considered sufficient for now. Structures defined in C-header files will be used to determine the values of the appropriate fields. The adnCouplerIndex is used for SFAS/MSUP routing purposes. This unfortunately only contains information of the chassis, slot and _line_ number (not processor). The user has to be aware of what line would map to the LT processor. Currently the line should be encoded as 255 for the LLT, and 383 for the ULT processor. Note that this information is likely to change.

This is the hex-dump that represents the SSUPLT processor control block entry. Each such entry contains information about the LT processor in which memory the block resides.

This table contains internal AAFD SWBB data structure, one entry per AAFD SWBB instance.

An entry in the adnAAFDMaintTable. There will be one entry for each AAFD SWBB instance.

This is the first part of internal AAFD data structure containing internal error counters and structures.

This is the second part internal AAFD data structure containing internal error counters and structures.

This is the third part internal AAFD data structure containing internal error counters and structures.

This is the fourth part of internal AAFD data structure containing internal error counters and structures.

This is the fifth part internal AAFD data structure containing internal error counters and structures.

This is the sixth part internal AAFD data structure containing internal error counters and structures.

This is the seventh part internal AAFD data structure containing internal error counters and structures.

This table contains internal AAFD SWBB data structure, one entry per Frame Relay logical line.

An entry in the adnAAFDVCCMaintTable. There will be one entry for each Frame Relay logical line.

This is the first part of internal data structure containing internal errors counters and structures concerning this Frame Relay logical line.

This is the second part of internal data structure containing internal errors counters and structures concerning this Frame Relay logical line.

This is the third part of internal data structure containing internal errors counters and structures concerning this Frame Relay logical line.

Entry AdnPssBWEntry

Each entry (row) in the adnPSSBWTable. There will be one entry per ifindex

This is the internal binary available bandwidth information received by Path Select for a particular ifindex.

This is adn pss ifindex.

This table contains various trace areas used by Path Select for maintenance/diagnostic purpose only.

Each entry (row) in the adnPssTraceTable.

This value is used to set Pss_print_flag to determine which printfs are allowed.

This is a binary value

The binary buffer value

This table contains various trace areas used by Path Select for maintenance/diagnostic purpose only.

Each entry (row) in the adnPssTraceTable.

Trace Index Number

This is the binary. All messages received from the Franp_si component are stored here

This table is to turn on and off the print capability Routes Agent for maintenance/diagnostic purpose only.

Each entry (row) in the adnRtsagtPrintFlagTable.

This value is used to set Rtsagt_print_flag to determine which printfs are allowed.

This table contains various trace areas used by Routes Agent for maintenance/diagnostic purpose only.

Each entry (row) in the adnRtsagtTraceTable.

Trace Index Number

This is the binary.

This table contains Link Control Block values

Entry in the adnRtsagtLinkCtrlBlkTable.

Routes agent link control block ifindex.

Routes agent lpx self

Routes Agent 0:user, 1 : network.

Routes agent hss : 1, tpx : 0, other : 2.

Routes agent Signal channel status received, sent, signal enabled, sig disabled, sig blocked, no. of sig states.

Routes agent states for L2 Interface Idle or link released, Waiting for establish, Link Established, Awaiting release conf, L2 flow controlled us, Number of L2 states.

Routes agent MH States, Add request sent to MH, MH link status down, Sent link up request, Link with MH is up, MH has sent XOFF, Local XOFF sent to MH, Number of MH states.

Routes agent state of l3 interface, L3 not yet established, Sent Establish Req, We sent Xoff to Remote, Remote sent Xoff to us, We sent block to Remote, Remote sent block to us, Link up in data xfer, Number of L3 states.

Routes agent state of Link Handler, Processing Add Request, Waiting for enable, Waiting for MDL confirm, Waiting TPX setup, Waiting TPX release, Waiting L2 establish, Waiting L3 establish, Wait for link up from MH, Wait for releases Link operational, L3 up, MH down on purpose, IACS is down, Number of LH states.

Routes agent Pointer to control Block of signal.

Routes agent lpx of lt.

Routes agent lpx for lt data transfer memory

Routes agent Signalling IFAP

Routes agent SUID

Routes agent negotiated pkt size with peer

Routes agent link handler version of peer

Routes agent time period of sending heartbeat

Routes agent if no heartbeat for this time

Routes agent information relevant to sig_if

Routes agent information relevant to l2_if

Routes agent information relevant to l3_if

Routes agent information relevant to mh_if

Routes agent information relevant to lh_main

Routes agent timer info

Routes agent next LCB in the list

Routes agent next LCB in the list

Routes agent durations for various timers

Routes agent set by layer2_id of Add channel

Routes agent set by l2_ctx.l2_ref of mdl_assign_conf

Routes agent IfIndex type

Routes agent trace containing the delay and monetary cost metrics per line. The first and third octet strings are fields which contain a number representing the type of cost (delay(3) and monetary(4)). The second and fourth octet strings contain the actual cost value for the cost type defined in the field before it.

Routes agent flag representing the status of the link dead timer on each line. A one indicates the timer is on and a zero indicates the timer is off. The link dead timer is a timer that starts when a line is set up and expires when there are no messages sent across the line for a period of time. If the timer expires the link is deemed dead and is reset. However, the timer is refreshed every time a message is sent across the link.

Entry in the adnRtsagtLocalAddrTable

Entry in the adnRtsagtLocalAddrTable

Routes agent Address Index.

Routes Agent address entry block

Routes Agent address entry block

Entry in the adnRtsagtTimerHdrTable

Entry in the adnRtsagtTimerHdrTable

Routes agent Timer Index.

Routes Agent Timer duration

Routes Agent Timer Purpose

Routes Agent Timer tobedeleted

Routes Agent Next timer pointer

Routes Agent Next timer pointer

This object provides a mechanism for controling the whole MSUP tool box setup. - default : the MSUP tool box configuration parameters are set to the default values. - temporary : the MSUP tool box configuration parameters have been personalized, but a CU restart will restore the default values. - permanent : the MSUP tool box configuration parameters have been personalized and saved in order to retrieve the personalization after CU cold or mild restarts. A set to permanent saves the setup for next restarts. A set to temporary keeps the current setup but deletes the previous save. A set to default restaures the default setup.

A set of adnMsupCtxEntry entries.

This object provides a mechanism to dump on the CU craft interface contexts in MSUP memory.

The types of contexts in MSUP that can be dumped : - chassisCtx(1) : context of a chassis - boardCtx(2) : context of a board - processorCtx(3) : context of a processor - aeiPortCtx(4) : context of an AEI port - atmCtx(5) : ATM init context - generalCtx(6) : general MSUP data context - nodeConfigCtx(7) : node system configuration context - nodeSystCtx(8) : node system contextual context - sessionCtx(9) : IACS session context - cuCtx(10) : CU management context

The index of a context.

This object provides a mechanism to print on the CU craft interface information about a context. - dump : dumps the content of a context, - address : displays the address of a context, - format : displays the context in a C format.

This object is a bitmap that enables to activate the printing of MSUP exchanges on the CU craft interface. bit val meaning --- ------------------------------------------------------- 1 displays exchanges with SMSUP 2 displays exchanges with ATMSUP 4 displays exchanges with APSUP 8 displays exchanges with CUSUP 16 displays exchanges with NMGS in fixed format 32 displays exchanges with FLS 64 displays exchanges with Debug Manager 128 displays traps sent to SFAS 256 displays localization service messages

This object is a bitmap that enables to activate the printing of MSUP exchanges on the CU craft interface. bit val meaning --- ------------------------------------------------------- 1 displays execution traces about coupler redundancy 2 displays execution traces about configuration 4 displays execution traces about clock synchronization 8 displays board automaton traces 16 displays processor automaton traces 32 displays execution traces about CU management 64 displays execution traces about coupler debug 128 displays execution traces about timer management

This object enable to active the display of STR received through SMSUP or APSUP from couplers on the CU craft interface

This object indicates wether the MSUP localization service writes into the MSUP HSS trace buffer.

This object indicates wether MSUP prints the HSS traces on the CU craft interface in real time.

This object indicates wether the MSUP HSS trace is frozen. On any CU restart this object is reset to the default value.

This object indicates wether the MSUP HSS trace is to be frozen on next MSUP STR.

Number of the STR on which to freeze the MSUP HSS trace. 0 is an unused STR number.

This object provides a mechanism to dump on the CU craft interface the formated content of the whole MSUP HSS trace buffer.

The size of the MSUP HSS trace buffer. A modification of this object can only be taken into account at the next start up.

This table is used by CVSI for the purpose of debugging.

An entry in the CVSI HSS Table.

This entry represents the current instance or index of the table. It is provided in order to be able to dump each instance of each object.

This object provides a mechanism for controlling Cvsis ability to enable/disable tracing of various types of messages. The following are the possible values it can hold. 0 - Trace disabled 1 - Trace CVSI Library information messages 2 - Trace CVSI Library Minor error messages 4 - Trace CVSI Library Major error messages 8 - Trace CVSI Library detailed messages 16 - Trace CVSI relay messages 32 - Trace CVSI Master messages 64 - Trace ATM Signalling messages 128 - Trace CLCS messages

This is the internal BINARY message trace entry maintained by CVSI.

This is the internal BINARY pointer to set of Counters maintained by CVSI.

CVSI global variables.

This object provides a mechanism for controlling Cvsis ability to print on the CU console various debugging information. The following are the possible values for this object. 0 - Print disabled 1 - Print CVSI Library information messages 2 - Print CVSI Library Minor error messages 4 - Print CVSI Library Major error messages 8 - Print CVSI Library detailed messages 16 - Print CVSI relay messages 32 - Print CVSI Master messages 64 - Print ATM Signalling messages 128 - Print CLCS messages

Indicates the number of active TDP Virtual Circuits in the current node.

This table is used to get Message handling entries values for Route Manager.

Each entry (row) in the adnRtsmgrTraceTable.

Trace Index Number.

This string displays a string of 36 bytes combination of Route Manager trace entry constants, trace entry variables, and time stamp.

This is the IP Routing Environmental Table

The IP Route Int Entry provides access to the CU TCP/UDP/IP stack information. It is recommended that the objects of this table be fetched with an SNMP get/getnext/etc. of all instances of the given object without any index postfix.

This object defines the Index into this table.

This object defines the ASCII string that includes the CU IP Interface description (similar to unix [netstat -i] command).

This object defines the ASCII string that includes the CU IP Forwarding memory cache (similar to unix [netstat -r] command).

This object defines the ASCII string that includes the CU IP/ TCP/UPD packet count statistics (similar to unix [netstat -s] command).

This object defines the ASCII string that includes the CU IP network sockets (similar to unix [netstat -a] command).

This object defines the ASCII string that includes the CU IP network connections (similar to unix [netstat -A] command).

This object defines the ASCII string that includes the CU IP network numbers (similar to unix [netstat -n] command).

This is the IP Routing Environmental Table

The IP Route Diag Entry defines IP Routing supplemental objects used to diagnose/trouble shoot IP Routing subsystem problems.

This object defines the Index into this table.

This object defines the print control flags bit mask used to enable printing debugging messages to the CU console screen. Each bit position is used to enable printing of processing different level of internal IP Routing processing messages: -- The hexidecimal bit positions are defined as follows: 0x0001 Do not print any diagnostic messages 0x0002 Print only NHP messages 0x0004 Print only GAT messages 0x0008 Print only SNMP messages 0x0010 Print only CONFIG messages 0x0020 Print NMGS FSM messages 0x0040 Print SFAS FSM messages 0x0080 Print RDSS FSM messages 0x0100 Print GATED FSM messages 0x0200 Print all ERROR messages 0x0400 Print all DEBUG messages 0x0800 Print ALL the above message types 0x1000 Activate GateD with its trace ON --

This table contains an array of records to those subsystems that have established IACS session with Routes Distribution.

Entry in the adnRdssRegistrationTable.

The LPX of subsystem which is registered to Routes Distribution.

ICS Reference number

This field identifies which SWBB (IPforwarding, ISNA, GDC, SFAS or PRTA) this registration entry is belong to.

This flag indicates whether the IACS session between Routes Distribution and the registered subsystem (IPforwarding, ISNA, GDC, SFAS or PRTA) in registration entry is congested or not.

This field identifies the sequence number used to send the last previous FAT message. The sequence number increments sequentially on every new FAT message sent. It will be rolled back to zero when reached maximum value.

This field identifies the sequence number used to send the last previous GAT message. The sequence number increments sequentially on every new GAT message sent. It will be rolled back to zero when reached maximum value.

This field identifies the sequence number used to send the last previous MAT message. The sequence number increments sequentially on every new MAT message sent. It will be rolled back to zero when reached maximum value.

This is bit-map field represents the statuses of acknowledgment from a previous transmitted FAT, GAT, or MAT message. Bit 0 represents FAT acknowledgment, bit 1 represents GAT acknowledgment, and bit 2 represents MAT acknowledgment. If a bit position has value of zero, it indicates the correspond acknowledgment message has not been received. When an acknowledgment message is received, its sequence number is compared with the correspond transmitted messages sequence number. If both are match, then the correspond Ack Flag bit will be set. If both are not match, then the received message will be ignored.

This field hold the sequesnce number of the last received valid Next-Hop message. It is used for handling duplicate received messages. This field is intialized to 0xff.

This field hold the sequesnce number of the last received valid LAT message. It is used for handling duplicate received messages. This field is intialized to 0xff.

This field hold the sequesnce number of the last received valid MAT message. It is used for handling duplicate received messages. This field is intialized to 0xff.

This is the address of the message buffer for sending data.

This field is used to indentify whether the traversing is currently on LPX, Ifindex or VC.

This field is used to identify the LPX of corresponding interface being traverse.

This field is bit-map defining what types of tables are to be provided to the registering subsystem. Table types include FAT, GAT, MAT, and etc.

This key is used for the purpose of distributing the entries from the GAT table when a SWBB subsystem has just register (just came up) with Routes Distribution. The Start Key is the key to the first entry sent on the previous message to aid in the scenario when retransmission of the previous message is required. Set Start key to NULL to indicate completed table has been sent, or table is empty. Set Start Key to KEY {Root} to start traversal. Set Start Key equal to End Key to indicate GAT table traversal is completed.

This key is used for the purpose of distributing the entries from the GAT table when a SWBB subsystem has just register (just came up) with Routes Distribution. The End Key is the key to the last GAT entry sent on the previous message, and is used to keep track of where in the GAT table to continue for the next message.

The GAT message queue contains linked list of updated entries. This start pointer marks an entry in the lists as beginning entry in the lists to be sent or is sending to the correspond IP Forwarding subsystem.

The FAT Entrance Key. This field is used to set the starting point to traverse the FAT table for this session.

The forwarding table contains data information to be forwarded, and status and control information relating to the entry itself for table book keeping purpose.

Entry in the adnRdssForwardingTable.

The IP address of the destination prefix.

This field represent the valid number of leading bits in the prefix of this address. It is the network IP mask.

This field represents the type of the destination IP address.

This is the same as the command field in the entry message header. Except when the value od this field is 255, then it is for internal used.

This field conveys the status information of the entry itself. It has dual functions and divided into two separated fields: Entry Status field and ACK count field.

This field represents the IP address of the directly connected router or the local IP address. If the adnRdssFatFlag is Local Host entry, then this field is Zero.

This longword is part of the three longwords which composes of forty eight 2-bit fields. Each 2-bits field represents the FSM of this entry to the corresponding IP Forwarding subsystem. The FAT Entry Processing FSM Control Block keeps track of which IP Forwarding this entry needed to be forwarding to, and which IP Forwarding this entry has been forwarded to, and which IP Forwarding has already acknowledged the reception of this entry.

This longword is part of the three longwords which composes of forty eight 2-bit fields. Each 2-bits field represents the FSM of this entry to the corresponding IP Forwarding subsystem. The FAT Entry Processing FSM Control Block keeps track of which IP Forwarding this entry needed to be forwarding to, and which IP Forwarding this entry has been forwarded to, and which IP Forwarding has already acknowledged the reception of this entry.

This longword is part of the three longwords which composes of forty eight 2-bit fields. Each 2-bits field represents the FSM of this entry to the corresponding IP Forwarding subsystem. The FAT Entry Processing FSM Control Block keeps track of which IP Forwarding this entry needed to be forwarding to, and which IP Forwarding this entry has been forwarded to, and which IP Forwarding has already acknowledged the reception of this entry.

This table contains all information associated with all the ifindexes, which are configured in the IP Forwarding subsystems.

Entry in the adnRdssGatIfindexTable.

The LPX of subsystem which is registered to Routes Distribution.

This is the unique identifier associated to the logical IP interface.

Type of LAT message.

Type of LAT command.

Status of the ifindex.

This field is the source address associated with the ifindex.

This field represents the valid number of leading bits in the prefix of the adnRdssGatIfLiiAddress. It is the network IP mask.

. Refer to RFC 1512 for the exhaustive list of the service types. We currently support only Frame Relay and AAL5/ATM.

This field represents the size of the MTU associated with this ifindex.

This field is used by IPFW and is passed as it is from RDSS to all other IP Forwarding subsystems.

This field represents the broadcast IP address associated with the Ifindex.

This is the interface cost associated with the ifindex.

This table contains all information associated with all the VCs, which are configured in the IP Forwarding subsystems.

Entry in the adnRdssGatVcTable.

This field represents the IP address of the directly connected router or the local IP address.

The LPX of subsystem which is registered to Routes Distribution.

This is the unique identifier associated to the VC.

This field represents the data link identifier (VPI/VCI for AAL5 or DLCI for Frame Relay for the Next-Hop under discussion.

Type of LAT message.

Type of LAT Vc command.

Status of Vc.

. Refer to RFC 1512 for the exhaustive list of the service types. We currently support only Frame Relay and AAL5/ATM.

This is the interface cost associated with the ifindex.

This field is the source address associated with the ifindex.

Each entry (row) in the adnRdssTraceTable

Each entry (row) in the adnRtsagtTraceTable.

LPX of registered subsystems.

Trace Index Number

This is the binary.